Exemplary embodiments relate to a multi-chip memory device, and more particularly to a multi-chip memory device which is capable of improving efficiency by operating only the remaining chips if some chips fail.
Size and weight of electronic devices are getting smaller and lighter in line with the technological developments in the semiconductor industry in response to the customer needs. One technique for meeting such needs in the semiconductor industry is the multi-chip packaging technique. The multi-chip packaging technique as implied by the name is a technique for forming a package having a plurality of semiconductor chips within it. Use of a multi-chip package provides advantages in terms of smaller size, lighter weight, and reduced mounting area as compared to use of several packages each having one semiconductor chip packaged therein.
When one or more chips in a conventional multi-chip package fail, all chips in the package including those that did not fail end up being not used due to problems existing in the process. For example, in a multi-chip memory device having four chips 1CE to 4CE packaged therein, even if only one of the chips 1CE to 4CE were to fail, the entire multi-chip memory device including the chips 1CE to 4CE is treated as a fail.